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ISL97651
Data Sheet March 15, 2007 FN7493.2
4-Channel Integrated LCD Supply
The ISL97651 represents a high power, integrated LCD supply IC targeted at large panel LCD displays. The ISL97651 integrates a high power, 4.4A boost converter for AVDD generation, an integrated VON charge pump, a VOFF charge pump driver, VON slicing circuitry and a buck regulator with 2A switch for logic generation. The ISL97651 have been designed for ease of layout and low BOM cost. Supply sequencing is integrated for both AVDD -> VOFF -> VON and AVDD/VOFF -> VON sequences. The TFT power sequence uses a separate enable to the logic buck regulator for maximum flexibility. Peak efficiencies are 90% for boost and 92% for buck while operating from a 4V to 5.5V input supply. The current mode buck offers superior line and load regulation. Available in the 36 Ld QFN package, the ISL97651 is specified for ambient operation over the -40C to +105C temperature range.
Features
* 4V to 5.5V input supply * AVDD boost up to 20V, with integrated 4.4A FET * Integrated VON charge pump, up to 34V out * VOFF charge pump driver, down to -18V * VLOGIC buck down to 1.2V, with integrated 2A FET * Automatic start-up sequencing - AVDD -> VOFF -> VON or AVDD/VOFF -> VON - Independent logic enable * VON slicing * Thermally enhanced thin QFN package (6mmx6mm) * Pb-free plus anneal available (RoHS compliant)
Applications
* LCD monitors (15"+) * LCD-TVs (40"+)
Pinout
ISL97651 (36 LD TQFN) TOP VIEW
29 CDEL 31 DELB 33 VIN2 32 CM1 34 FBB 30 ENL 36 NC 28 NC 35 EN
* Notebook displays (up to 16") * Industrial/medical LCD displays
Ordering Information
27 AGND 26 PGND1 25 PGND2 24 VINL
VIN1 1 LX1 2 LX2 3 CB 4 LXL 5 VSUP 6 FBL 7 CM2 8 CTL 9 NC 10 COM 12 POUT 13 C1- 14 C1+ 15 C2- 16 C2+ 17 DRN 11 NC 18 THERMAL PAD
PART NUMBER (Note) ISL97651ARTZ-T
PART MARKING ISL976 51ARTZ
TAPE & PACKAGE PKG. REEL (Pb-Free) DWG. # 13" 36 Ld 6x6 (4k pcs) TQFN 13" 36 Ld 6x6 (1k pcs) TQFN L36.6x6 L36.6x6
ISL97651ARTZ-TK ISL976 51ARTZ
23 NOUT 22 PGND3 21 FBN 20 VREF 19 FBP
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97651
Absolute Maximum Ratings (TA = +25C)
Maximum Pin Voltages, All Pins Except Below . . . . . . . . . . . . . 6.5V LX1, LX2, VSUP, NOUT, DELB, C1-, C2- . . . . . . . . . . . . . . . . .24V C1- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13V DRN, COM, POUT, C1+, C2+ . . . . . . . . . . . . . . . . . . . . . . . . .36V CB-VINL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) 6x6 QFN Package (Notes 1, 2) . . . . . . 30 2.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Power Dissipation TA +25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3W TA = +70C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8W TA = +85C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3W TA = +100C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8W
Recommended Operating Conditions
Input Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . 4V to 5.5V Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . . . . . . . +20V VON Output Range, VON . . . . . . . . . . . . . . . . . . . . . . +15V to +32V VOFF Output Range, VOFF . . . . . . . . . . . . . . . . . . . . . . -15V to -5V Logic Output Voltage Range, VLOGIC . . . . . . . . . . . +1.5V to +3.3V Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 x 10F Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3H to 10H Output Capacitance, COUT . . . . . . . . . . . . . . . . . . . . . . . . 2 x 22F Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3H to 10H Operating Ambient Temperature Range . . . . . . . . -40C to +105C Operating Junction Temperature . . . . . . . . . . . . . . -40C to +125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. +150C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150C junction may trigger the shutdown of the device even before +150C, since this number is specified as typical.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER SUPPLY PINS VIN VINL VSUP IVIN
VIN = 5V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over-temperature from -40C to +105C, unless otherwise stated. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Supply Voltage (VIN1 and VIN2) Logic Supply Voltage Charge Pumps and VON Slice Positive Supply Quiescent Current into VIN Enabled, No switching Disabled
4 4 4
5 5
5.5 5.5 20 3 10
V V V mA A mA A mA A V V V V kHz
IINL
Logic Supply Current
Enabled, No switching Disabled
0.4
1.0 10 0.5 10
ISUP
VSUP Supply Current
Enabled, No switching and VPOUT = VSUP Disabled
VLOR VLOF VREF
Undervoltage lockout threshold Undervoltage lockout threshold Reference Voltage
VIN rising VIN falling TA = +25C
2.0 1.9 1.19 1.187
2.75 2.2 1.205 1.205 1200
2.9 2.5 1.235 1.238 1400
fOSC
Oscillator Frequency
1010
AVDD BOOST DMax, Maximum Duty Cycle: Minimum 84% VBOOST IBOOST Boost Output Range Boost Switch Current Current limit 1.25*VIN 4.4 4.8 20 6.3 V A
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ISL97651
Electrical Specifications
PARAMETER EFFBOOST rDS(ON) VBOOST/VIN VBOOST/IOUT VFBB VIN = 5V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over-temperature from -40C to +105C, unless otherwise stated. (Continued) CONDITIONS See graphs and component recommendations MIN TYP 90 70 PI mode, R1 = 10k and C3 = 4.7nF over a load range of 0mA to 300mA (tested), 0-ILIMIT_ONSET (by design) TA = +25C 1.192 1.188 ACCBOOST tSS AVDD Output Accuracy Soft-start Period for AVDD TA = +25C CDEL = 220nF -1.5 9.6 0.4 0.1 1.205 1.205 100 1.5 0.5 1.218 1.222 +1.5 MAX UNIT % m %/V % V V % ms
DESCRIPTION Peak Efficiency Switch ON-Resistance Line Regulation Load Regulation Boost Feedback Voltage
VLOGIC BUCK DMAX_buck typical maximum duty cycle = 0.85*(VINL-ILOAD*0.3) ILOAD_min, Minimum 1mA for VINL-VBUCK >1.5V, 5mA otherwise VBUCK IBUCK EFFBUCK RDS-ONBK VBUCK/VIN VBUCK/IOUT VFBL Buck Output Voltage Buck Switch Current Peak Efficiency Switch ON-Resistance Line Regulation Load Regulation FBL Regulation Voltage PI mode, R1 = 2k and C3 = 4.7nF over a load range of 0mA to 300mA (tested), 0-ILIMIT_ONSET (by design) IDRVL = 1mA, TA = +25C IDRVL = 1mA ACCLOGIC tSS(L) VLOGIC Output Accuracy Soft-Start Period for V(Logic) TA = +25C C(VREF) = 220nF (Note - no soft-start if EN asserted HIGH before ENB) 1.176 1.174 -2 0.5 Output current = 0.5A Current limit See graphs and component recommendations VREF 2.0 2.7 92 200 0.1 0.04 1.2 1.2 455 1 0.5 1.224 1.226 +2 4 V A % m %/V % V V % ms
NEGATIVE (VOFF) CHARGE PUMP VOFF ILOAD_NCP_MIN rON(NOUT)H rON(NOUT)L IPU(NOUT)LIM IPD(NOUT)LIM I(NOUT)LEAK VFBN VOFF Output Voltage Range External Load Driving Capability High-Side Driver ON-Resistance at NOUT Low-Side Driver ON-Resistance at NOUT Pull-up Current Limit in NOUT Pull-down Current Limit in NOUT Leakage Current in NOUT FBN Regulation Voltage 2X Charge Pump VSUP > 5V I(NOUT) = +60mA I(NOUT) = -60mA V(NOUT) = 0V to V(SUP)-0.5V V(NOUT) = 0.36V to V(VSUP) V(FBN) < 0 or EN = LOW IDRVN = 0.2mA, TA = +25C IDRVN = 0.2mA ACCN D_NCP_max rPD(FBN)OFF VOFF Output Accuracy Max Duty Cycle of the Negative Charge Pump Pull-Down Resistance, Not Active I(FBN) = 500A 2 IOFF = 1mA, TA = +25C -2 0.173 0.171 -3 50 3 4 0.203 0.203 60 270 -200 -60 2 0.233 0.235 +3 -VSUP+1.4V 30 10 5 0 V mA mA mA A V V % % k
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ISL97651
Electrical Specifications
PARAMETER VIN = 5V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over-temperature from -40C to +105C, unless otherwise stated. (Continued) CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
POSITIVE (VON) CHARGE PUMP VON ILOAD_PCP_MIN VON Output Voltage Range External Load Driving Capability 2X or 3X Charge Pump VON = 25V (2X Charge Pump) VON = 34V (3X Charge Pump) rON(VSUP_SW) rON(C1/2-)H rON(C1/2-)L IPU(VSUP_SW) IPU(C1/2-) IPD(C1/2-) I(POUT)LEAK VFBP ON-Resistance of VSUP Input Switch I(SWITCH) = +40mA High-Side Driver ON-Resistance at C1- and C2Low-Side Driver ON-Resistance at C1- and C2Pull-Up Current Limit in VSUP Input Switch I(C1/2-) = +40mA I(C1/2-) = -40mA V(C2+) = 0V to V(SUP) - 0.4V - V(DIODE) 40 40 VSUP + 2V 20 20 10 10 4 100 100 -100 -5 1.176 1.172 -2 50 I(DIODE) = +40mA 600 850 1.2 1.2 -40 5 1.224 1.228 +2 17 20 7 34 V mA mA mA mA mA A V V % % mV
Pull-Up Current Limit in C1- and C2- V(C1/2-) = 0V to V(VSUP) - 0.4V Pull-Down Current Limit in C1- and C2Leakage Current in POUT FBP Regulation Voltage V(C1/2-) = 0.2V to V(VSUP) EN = LOW IDRVP = 0.2mA, TA = +25C IDRVP = 0.2mA
ACCP D_PCP_max V(DIODE) ENABLE INPUTS VHI-EN VLO_EN IEN_pd VHI-ENL VLO-ENL IENL_pd
VON Output Accuracy Max Duty Cycle of the Positive Charge Pump Internal Schottky Diode Forward Voltage
ION = 1mA, TA = +25C
Enable "HIGH" Enable "LOW" Enable Pin Pull-Down Current Logic Enable "HIGH" Logic Enable "LOW" Logic Enable Pin Pull-Down Current VENL > VLO_ENL VEN > VLO_EN
2.2 0.8 25 2.2 0.8 25
V V A V V A
VON SLICE Positive Supply = V(POUT) I(POUT)_SLICE VON slice Current from POUT Supply CTL = VDD, sequence complete CTL = AGND, sequence complete rON(POUT-COM) rON(DRN-COM) rON_COM VLO VHI ON-Resistance between POUT COM ON-Resistance between DRN COM ON-Resistance between COM and PGND3 CTL Input LOW Voltage CTL Input HIGH Voltage CTL = VDD, sequence complete CTL = ACGND, sequence complete During start-up sequence VIN = 4V to 5.5V VIN = 4V to 5.5V 2.2 200 100 90 5 30 500 200 120 10 60 1500 0.8 A A V V
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FN7493.2 March 15, 2007
ISL97651
Electrical Specifications
PARAMETER VIN = 5V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over-temperature from -40C to +105C, unless otherwise stated. (Continued) CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
FAULT DETECTION THRESHOLDS T_off Vth_AVDD(FBB) Vth_VLOGIC(FBL) Vth_POUT(FBP) Vth_NOUT(FBN) tFD Thermal Shut-Down (latched and reset by power cycle or EN cycle) AVDD Boost Short Detection VLOGIC Buck Short Detection Temperature rising V(FBB) falling less than V(FBL) falling less than 150 0.9 0.9 0.9 0.4 52 C V V V V ms
POUT Charge Pump Short Detection V(FBP) falling less than NOUT Charge Pump Short Detection V(FBN) rising more than Fault Delay Time to Chip Turns Off CDEL = 220nF
START-UP SEQUENCING tSTART-UP IDELB_ON Enable to AVDD Start Time DELB Pull-Down Current or Resistance when Enabled by the Start-Up Sequence DELB Pull-Down Current or Resistance when Disabled AVDD to VOFF VOFF to VON Delay VON to VON-SLICE Delay CDEL = 220nF VDELB > 0.9V VDELB < 0.9V VDELB < 20V CDEL = 220nF CDEL = 220nF CDEL = 220nF 9 20 17 36 1000 80 50 1326 70 1750 500 ms A nA ms ms ms
IDELB_OFF tVOFF tVON tVON-SLICE
Typical Performance Curves
100 AVDD LOAD REGULATION (%) 0.10 0.05 80 EFFICIENCY (%) VIN = 5V, AVDD = 15V 60 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 0 200 400 600 800 1000 0 200 400 IOUT (mA) 600 800 IOUT (mA) 1000 1200 VIN = 5V, AVDD = 15V
40
20
0
FIGURE 1. AVDD EFFICIENCY vs IOUT
FIGURE 2. AVDD LOAD REGULATION vs IOUT
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ISL97651 Typical Performance Curves (Continued)
L1 = 10H, COUT = 40F, CM1 = 4.7nF, RM1 = 10k CH1 = AVDD(200mV/DIV), CH2 = IAVDD(200mA/DIV) 100 90 VLOGIC EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 1ms/DIV 0 500 1000 1500 2000 VIN = 5V, VLOGIC = 3.3V
OUTPUT CURRENT (mA)
FIGURE 3. AVDD TRANSIENT RESPONSE
FIGURE 4. VLOGIC EFFICIENCY vs OUTPUT CURRENT
L2 = 6.8H, COUT = 30F, CM2 = 4.7nF, RM2 = 10k, 0.1 VIN = 5V, VLOGIC = 3.3V VLOGIC LOAD REGULATION (%) 0 -0.1 -0.2 -0.3 -0.4 -0.5 CH1 = VLOGIC(50mV/DIV), CH2 = ILOGIC(200mA/DIV)
0
500
1000
1500
2000
2500 1ms/DIV
OUTPUT CURRENT (mA)
FIGURE 5. VLOGIC LOAD REGULATION vs OUTPUT CURRENT
FIGURE 6. VLOGIC TRANSIENT RESPONSE
0 VON LOAD REGULATION (%) -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 0 10 20 30 ION (mA) 40 50 60 VON = 25V VLOGIC LOAD REGULATION (%)
0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 -0.09 -0.10 0 200 400 600 800 1000 1200 1400 1600 1800 2000 OUTPUT CURRENT(mA) VIN = 5V, VLOGIC = 3.3V
FIGURE 7. VON LOAD REGULATION vs ION
FIGURE 8. VLOGIC LOAD REGULATION vs OUTPUT CURRENT
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FN7493.2 March 15, 2007
ISL97651 Typical Performance Curves (Continued)
CH1 = COM(10V/DIV), CH2 = CTL(2V/DIV) CH1 = CDLY, CH2 = VREF, CH3 = VLOGIC, CH4 = VON, R1 = AVDD, R2 = AVDD_DELAY, R3 = VOFF
4ms/DIV
FIGURE 9. VON-SLICE CIRCUIT OPERATION
FIGURE 10. START-UP SEQUENCE
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FN7493.2 March 15, 2007
ISL97651 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10, 18, 28, 36 11 12 13 14 15 16 17 19 20 21 22 23 24 25, 26 27 29 30 31 32 33 34 35 (Exposed Die Plate) PIN NAME VIN1 LX1 LX2 CB LXL VSUP FBL CM2 CTL NC DRN COM POUT C1C1+ C2C2+ FBP VREF FBN PGND3 NOUT VINL PGND2, 1 AGND CDEL ENL DELB CM1 VIN2 FBB EN N/A Input voltage, connect to pin 33 (VIN2) Internal boost switch connection Internal boost switch connection Logic buck, boost strap pin Buck converter output Positive supply for charge pumps Logic buck feedback pin Buck compensation network pin Input control for VON slice output No connect. Connect to die pad and GND for improved thermal efficiency. Lower reference voltage for VON slice output VON slice output: when CTL = 1, COM is connected to SRC through a 5 resistor; when CTL = 0, COM is connected to DRN through a 30 resistor. Positive charge pump out Charge pump capacitor 1, negative connection Charge pump capacitor 1, positive connection Charge pump capacitor 2, negative connection Charge pump capacitor 2, positive connection Positive charge pump feedback pin Reference voltage Negative charge pump feedback pin Power ground for VOFF, VON and VON slice Negative charge pump output Logic buck supply voltage Boost power grounds Signal ground pin Delay capacitor for start up sequencing, soft-start and fault detection timers. Buck enable for VLOGIC output Open drain NFET output to drive optional AVDD delay PFET Boost compensation network pin Input voltage, connect to pin 1 (VIN1) Boost feedback pin Enable for Boost, charge pumps and VON slice (independent of ENL). Connect exposed die plate on rear of package to ACGND and the PGND1, 2 pins. See "Layout Recommendation" on page 18 for PCB layout thermal considerations. DESCRIPTION
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FN7493.2 March 15, 2007
ISL97651 Block Diagram
VREF
CM1 FBB VREF + VOLTAGE FEEDBACK
SAWTOOTH GENERATOR SLOPE COMPENSATION REFERENCE AND BIAS THRESHOLDS AND BIAS CURRENT FEEDBACK LX1 LX2
BUFFER
UVLO COMPARATOR +
CONTROL LOGIC
RSENSE PGND1 PGND2
0.75VREF 1.2MHz OSCILLATOR
PGND3 VIN1, VIN2 EN CDEL ENL SEQUENCE AND FAULT CONTROL CURRENT LIMIT COMPARATOR CURRENT LIMIT THRESHOLD DELB ACGND
VINL VSUP NOUT CURRENT LIMIT COMPARATOR + CURRENT LIMIT THRESHOLD BUFFER CURRENT FEEDBACK NOUT CONTROL
CB
LXL CONTROL LOGIC VOLTAGE FEEDBACK
CM2
FBN 0.2V
+
SLOPE COMPENSATION SAWTOOTH GENERATOR
+ VREF
FBL
UVLO COMPARATOR + 0.4V 0.75 VREF +
UVLO COMPARATOR POUT CONTROL VSUP + 0.75 VREF
FBP VREF
+
POUT VSUP
C1-
C1+
POUT C2+
C2-
DRN
CTL
COM
FIGURE 11. BLOCK DIAGRAM
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FN7493.2 March 15, 2007
ISL97651 Typical Application Diagram
VIN R18 4.7 C1 2.2 C3 4.7nF L1 6.8F VIN1 VIN2 R1 10k PGND1 BOOST PGND2 ENB EN CDEL C6 0.22F BIAS AND SEQUENCE CONTROL VREF C20 820p R6 40k FBB DELB R20 500k R5 5k C18* LX2 R17* CM1 LX1 D1 C2 40F AVDD R3 55k AVDD_DELAY 15V C4 OPEN R4 300k C5 1F
C11 220nF
C19 100p R7 328k D2 D3 -8V VOFF C13 470nF
FBN PGND3 VOFF CP NOUT
C12 220nF VSUP
C1+ C7 220nF C8 220nF C1C2+ C2VON CP FBP POUT
C21 100p R8 983k R9 50k C22 2.2nF C14 470nF R10 68k R11 C15 0.1F 1k +25V VON
DRN VON SLICE CTL COM VINL CB C10 10F C9 4.7nF R2 2k ENL FBL AGND CM2 LXL BUCK
R12
VON SLICE R13 100k C16 1F D4 L2 6.8H R14 2k R15 1.2k
TO GATE DRIVER IC
3.3V VLOGIC C17 20F
*Open component positions.
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FN7493.2 March 15, 2007
ISL97651 Applications Information
The ISL97651 provides a complete power solution for TFT LCD applications. The system consists of one boost converter to generate the AVDD voltage for column drivers, one buck converter to provide voltage to logic circuit in the LCD panel, one integrated VON charge pump and one VOFF linear-regulator controller to provide the voltage to row drivers. This part also integrates VON-slice circuit which can help to optimize the picture quality. With the high output current capability, this part is ideal for big screen LCD TV and monitor panel application. The integrated boost converter and buck converter operate at 1.2MHz which can allow the use of multilayer ceramic capacitors and low profile inductor which result in low cost, compact and reliable system. The logic output voltage is independently enabled to give flexibility to the system designers. This restricts the maximum output current (average) based on Equation 3:
I L V IN I OMAX = I LMT - -------- x -------- 2 VO
(EQ. 3)
Where IL is peak to peak inductor ripple current, and is set by Equation 4:
V IN D I L = --------- x ---L fS
(EQ. 4)
where fS is the switching frequency (1.2MHz). Table 1 gives typical values (margins are considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, fS and IOMAX:
TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION VIN (V) 4 4 4 5 5 5 VO (V) 9 12 15 9 12 15 L (H) 6.8 6.8 6.8 6.8 6.8 6.8 FS (MHz) 1.2 1.2 1.2 1.2 1.2 1.2 IOMAX (mA) 1661 1173 879 2077 1466 1099
Boost Converter
The boost converter is a current mode PWM converter operating at a fixed frequency of 1.2MHz. It can operate in both discontinuous conduction mode (DCM) at light load and continuous mode (CCM). In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by Equation 1:
V BOOST 1 ----------------------- = -----------1-D V IN
Boost Converter Input Capacitor
(EQ. 1)
Where D is the duty cycle of the switching MOSFET Figure 11 shows the functional block diagram of the boost regulator. It uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60k is recommended. The boost converter output voltage is determined by Equation 2:
( R3 + R5 ) V BOOST = ------------------------- x V REF R5
An input capacitor is used to suppress the voltage ripple injected into the boost converter. A ceramic capacitor with capacitance larger than 10F is recommended. The voltage rating of input capacitor should be larger than the maximum input voltage. Examples of recommended capacitors are given in Table 2 below.
TABLE 2. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION CAPACITOR 10F/16V 10F/10V 22F/10V SIZE 1206 0805 1210 VENDOR TDK Murata Murata PART NUMBER C3216X7R1C106M GRM21BR61A106K GRB32ER61A226K
Boost Inductor
The boost inductor is a critical component which influences the output voltage ripple, transient response, and efficiency. Values of 3.3H to 10H are to match the internal slope compensation. The inductor must be able to handle without saturating the following average and peak current:
IO I LAVG = -----------1-D I L I LPK = I LAVG + -------2
(EQ. 2)
The current through the MOSFET is limited to a minimum of 4.4APEAK (maximum values can be up to 6.3APEAK.
(EQ. 5)
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ISL97651
Some inductors are recommended in Table 3.
TABLE 3. BOOST INDUCTOR RECOMMENDATION INDUCTOR DIMENSIONS (mm) VENDOR PART NUMBER DO3316P-682ML CDR10D48MNNP-100NC
Table 5 shows some selections of output capacitors.
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION CAPACITOR 10F/25V 10F/25V SIZE 1210 1210 VENDOR TDK Murata PART NUMBER C3225X7R1E106M GRM32DR61E106K
6.8H/ 12.95x9.4x5.21 Coilcraft 4.6APEAK 10H/ 5.5APEAK 5.2H/ 4.55APEAK 10x10x5 10x10.1x3.8 Sumida
PI Loop Compensation (Boost Converter)
Cooper CD1-5R2 Bussmann
Rectifier Diode (Boost Converter)
A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The reverse voltage rating of this diode should be higher than the maximum output voltage. The rectifier diode must meet the output current and peak inductor current requirements. Table 4 shows some recommendations for boost converter diode.
TABLE 4. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION DIODE SS23 MBRS340 SL23 VR/IAVG RATING 30V/2A 40V/3A 30V/2A PACKAGE SMB SMC SMB VENDOR Fairchild Semiconductor International Rectifier Vishay Semiconductor
The boost converter of ISL97651 can be compensated by a RC network connected from CM1 pin to ground. C3 = 4.7nF and R1 = 10k RC network is used in the demo board. A higher resistor value can be used to lower the transient overshoot - however, this may be at the expense of stability to the loop. The stability can be examined by repeatedly changing the load between 100mA and a max level that is likely to be used in the system being used. The AVDD voltage should be examined with an oscilloscope set to AC 100mV/div and the amount of ringing observed when the load current changes. Reduce excessive ringing by reducing the value of the resistor in series with the CM1 pin capacitor.
Boost Converter Feedback Resistors and Capacitor
An RC network across feedback resistor R5 may be required to optimize boost stability when AVDD voltage is set to less than 12V. This network reduces the internal voltage feedback used by the IC. This RC network sets a pole in the control loop. This pole is set to approximately fp = 10kHz for COUT = 10F and fp = 4kHz for COUT = 30F. Alternatively, adding a small capacitor (20-100pF) in parallel with R5 (i.e. R17 = short) may help to reduce AVDD noise and improve regulation, particularly if high value feedback resistors are used.
1 1 -1 R17 = ------------------------ - --------- 0.1 x R5 R3 1 C18 = -----------------------------------------------------( 2 x 3.142 x fp x R5 )
Output Capacitor
The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor.
IO V O - V IN 1 V RIPPLE = I LPK x ESR + ----------------------- x --------------- x --f C V
O OUT s
(EQ. 7)
(EQ. 8)
Cascaded MOSFET Application
(EQ. 6)
For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. Note: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across then increases. COUT in Equation 6 assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at 0V.
An 20V N-channel MOSFET is integrated in the boost regulator. For the applications where the output voltage is greater than 20V, an external cascaded MOSFET is needed, as shown in Figure 12. The voltage rating of the external MOSFET should be greater than AVDD.
12
FN7493.2 March 15, 2007
ISL97651
VIN AVDD
potential for noise being coupled into the feedback pin. A resistor network in the order of 1k is recommended.
Buck Converter Input Capacitor
LX1, LX2 FBB INTERSIL ISL97651
The capacitor should support the maximum AC RMS current which happens when D = 0.5 and maximum output current.
I ACRMS ( C IN ) = D ( 1 - D ) IO
(EQ. 13)
Where IO is the output current of the buck converter. Table 6 shows some recommendations for input capacitor.
TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION FIGURE 12. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS CAPACITOR 10F/16V SIZE 1206 0805 1210 VENDOR TDK Murata Murata PART NUMBER C3216X7R1C106M GRM21BR61A106K C3225X7R1C226M
Buck Converter
The buck converter is the step down converter, which supplies the current to the logic circuit of the LCD system. The ISL97651 integrates an 20V N-Channel MOSFET to save cost and reduce external component count. In the continuous current mode, the relationship between input voltage and output voltage is shown in Equation 9:
V LOGIC --------------------- = D V IN
10F/10V 22F/16V
Buck Inductor
An inductor value in the range 3.3H to 10H is recommended for the buck converter. Besides the inductance, the DC resistance and the saturation current should also be considered when choosing buck inductor. Low DC resistance can help maintain high efficiency, and the saturation current rating should be at least 2A. Table 7 shows some recommendations for buck inductor.
TABLE 7. BUCK INDUCTOR RECOMMENDATION INDUCTOR 4.7H/2.7APEAK 6.8H/3APEAK DIMENSIONS (mm) VENDOR 5.7x5.0x4.7 7.3x6.8x3.2 Murata TDK PART NUMBER LQH55DN4R7M01K RLF7030T-6R8M2R8 DO3308P-103
(EQ. 9)
Where D is the duty cycle of the switching MOSFET. Because D is always less than 1, the output voltage of buck converter is lower than input voltage. The peak current limit of buck converter is set to 2A, which restricts the maximum output current (average) based on the Equation 10:
I OMAX = 2A - I pp
(EQ. 10)
10H/2.4APEAK 12.95x9.4x3.0 Coilcraft
Where IPP is the ripple current in the buck inductor as the Equation 11:
V LOGIC I pp = --------------------- ( 1 - D ) L fs
Rectifier Diode (Buck Converter)
A Schottky diode is recommended due to fast recovery and low forward voltage. The reverse voltage rating should be higher than the maximum input voltage. The peak current rating is 2A, and the average current should be as the Equation 14:
I AVG = ( 1 - D )*I o (EQ. 14)
(EQ. 11)
Where L is the buck inductor, fs is the switching frequency (1.2MHz).
Feedback Resistors
The buck converter output voltage is determined by the Equation 12:
R 14 + R 15 V LOGIC = -------------------------- x V REF R 15
Where IO is the output current of buck converter. Table 8 shows some diode recommended.
TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION
(EQ. 12)
DIODE PMEG2020EJ SS22
VR/IAVG RATING 20V/2A 20V/2A
PACKAGE SOD323F SMB
VENDOR Philips Semiconductors Fairchild Semiconductor
Where R14 and R15 are the feedback resistors of buck converter to set the output voltage current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the 13
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ISL97651
Output Capacitor (Buck Converter)
Four 10F or two 22F ceramic capacitors are recommended for this part. The overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer.
TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION CAPACITOR 10F/6.3V 10F/6.3V 22F/6.3V 100F/6.3V SIZE 0805 0805 1210 1206 VENDOR TDK Murata TDK Murata PART NUMBER C2012X5R0J106M GRM21BR60J106K C3216X5R0J226M GRM31CR60J107M
The pumps use pulse width modulation to adjust the pump period, depending on the load present. The pumps can provide 30mA for VOFF and 20mA for VON. The positive charge pump can generate double or triple VSUP voltage depending on the configuration of C2+ and C2- pins. If the C2+ pin connects to C1+, it is the voltage doubler, and if C2+ connects C2- via a capacitor, it configured a voltage tripler.
Positive Charge Pump Design Consideration
The positive charge pump integrates all the diodes (D1, D2 and D3 shown in the block diagram in Figure 13) required for x2 (VSUP doubler) and x3 (VSUP tripler) modes of operation. During the chip start-up sequence the mode of operation is automatically detected when the charge pump is enabled. With both C7 and C8 present, the x3 mode of operation is detected. With C7 present, C8 open and with C1+ shorted to C2+, the x2 mode of operation will be detected. Due to the internal switches to VSUP (M1, M2 and M3), POUT is independent of the voltage on VSUP until the charge pump is enabled. This is important for TFT applications where the negative charge pump output voltage (VOFF) and AVDD supplies need to be established before POUT. The maximum POUT charge pump current can be estimated from Equation 15 assuming a 50% switching duty:
I MAX ( 2x ) min of 50mA or 2 * V SUP - 2 * V DIODE ( 2 * I MAX ) - V ( V ON ) ---------------------------------------------------------------------------------------------------------------------- * 0.95A ( 2 * ( 2 * R ONH + R ONL ) ) (EQ. 15) I MAX ( 3x ) min of 50mA or 3 * V SUP - 3 * V DIODE ( 2 * I MAX ) - V ( V ON ) ---------------------------------------------------------------------------------------------------------------------- * 0.95V ( 2 * ( 3 * R ONH + 2 * R ONL ) )
PI Loop Compensation (Buck Converter)
The buck converter of ISL97651 can be compensated by a RC network connected from CM2 pin to ground. C9 = 4.7nF and R2 = 2k RC network is used in the demo board. The larger value resistor can lower the transient overshoot, however, at the expense of stability of the loop. The stability can be optimized in a similar manner to that described in "PI Loop Compensation (Boost Converter)" on page 12.
Bootstrap Capacitor (C16)
This capacitor is used to provide the supply to the high driver circuitry for the buck MOSFET. The bootstrap supply is formed by an internal diode and capacitor combination. A 1F is recommended for ISL97651. A low value capacitor can lead to overcharging and in turn damage the part. If the load is too light, the on-time of the low side diode may be insufficient to replenish the bootstrap capacitor voltage. In this case, if VIN - VBUCK < 1.5V, the internal MOSFET pullup device may be unable to turn-on until VLOGIC falls. Hence, there is a minimum load requirement in this case. The minimum load can be adjusted by the feedback resistors to FBL. The bootstrap capacitor can only be charged when the higher side MOSFET is off. If the load is too light which can not make the on time of the low side diode be sufficient to replenish the boot strap capacitor, the MOSFET can't turn on. Hence there is minimum load requirement to charge the bootstrap capacitor properly.
Note: VDIODE (2 * IMAX) is the on-chip diode voltage as a function of IMAX and VDIODE (40mA) < 0.7V. In voltage doubler configuration, the maximum VON is as given by Equation 16:
V ON_MAX(2x) = 2 * ( V SUP - V DIODE ) - 2 * I OUT * ( 2 * r ONH + r ONL ) (EQ. 16)
For Voltage Tripler:
V ON_MAX(3x) = 3 * ( V SUP - V DIODE ) - 2 * I OUT * ( 3 * r ONH + 2 * r ONL ) (EQ. 17)
Linear-Regulator Controllers (VON and VOFF)
The ISL97651 include 2 independent charge pumps (see Figure 13). The negative charge pump inverters the VSUP voltage and provides a regulated negative output voltage. The positive charge pump doubles or triples the VSUP voltage and provides a regulated positive output voltage. The regulation of both the negative and positive charge pumps is generated by internal comparator that senses the output voltage and compares it with the internal reference.
VON output voltage is determined by Equation 18:
R 8 V ON = V FBP * 1 + ------ R 9
(EQ. 18)
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ISL97651
External Connections and Components x2 Mode x3 Mode Both
VSUP M2 C1C7 C1+ VSUP M1
M4
Control 1.2MHz 0.9V
D3
D2
D1
POUT C14
VSUP Error M3 VREF FB
C2+ C8 C2C21 R8
M5
FBP
C22
R9
FIGURE 13. VON FUNCTION DIAGRAM
Negative Charge Pump Design Consideration
The negative charge pump consists of an internal switcher M1, M2 which drives external steering diodes D2 and D3 via a pump capacitor (C12) to generate the negative VOFF supply. An internal comparator (A1) senses the feedback voltage on FBN and turns on M1 for a period up to half a CLK period to maintain V(FBN) in regulated operation at 0.2V. External feedback resistor R6 is referenced to VREF. Faults on VOFF which cause VFBN to rise to more than 0.4V, are detected by comparator (A2) and cause the fault detection system to start a fault ramp on CDLY pin which will cause the chip to power down if present for more than the time TFD (see "Electrical Specification" on page 2 and also Figure 15). The maximum VOFF output voltage of a single stage charge pump is:
V OFF_MAX ( 2x ) = - V SUP+ V DIODE+ 2* I OUT* ( r ON( NOUT )H +r ON ( NOUT )L (EQ. 19)
R6 and R7 in the "Typical Application Diagram" on page 10 determine VOFF output voltage.
R7 R7 V OFF = V FBN * 1 + ------- - V REF * ------- R6 R6
(EQ. 20)
Improving Charge Pump Noise Immunity
Depending on PCB layout and environment, noise pick-up at the FBP and FBN inputs, which may degrade load regulation performance, can be reduced by the inclusion of capacitors across the feedback resistors (e.g. in the "Typical Application Diagram" on page 10, C21 and C22 for the positive charge pump). Set R6 * C20 = R7 * C19 with C19 ~ 100pF.
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ISL97651
VREF A2 FAULT 0.4V FBN A1 0.2V VDD VSUP C20 820pF R6 40k R7 328k C19 100pF
1.2MHz
STOP
M2 C12 220nF D2 VOFF (-8V) D3 C13 470nF
CLK NOUT
EN
PWM CONTROL
M1 PGND
FIGURE 14. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
VON Slice Circuit
The VON Slice Circuit functions as a three way multiplexer, switching the voltage on COM between ground, DRN and SRC, under control of the start-up sequence and the CTL pin. During the start-up sequence, COM is held at ground via an NDMOS FET, with ~1k impedance. Once the start-up sequence has completed, CTL is enabled and acts as a multiplexer control such that if CTL is low, COM connects to DRN through a 30 internal MOSFET, and if CTL is high, COM connects to POUT internally via a 5 MOSFET. The slew rate of start-up of the switch control circuit is mainly restricted by the load capacitance at COM pin as Equation 21:
Vg V ------- = -----------------------------------( R i || R L ) x C L t (EQ. 21)
Start-Up Sequence
Figure 15 shows a detailed start up sequence waveform. For a successful power up, there should be 6 peaks at VCDLY. When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled. When the input is higher than 2.75V; if either EN or ENL is H, VREF turns on. If ENL is H, VLOGIC turns on. If EN is H, an internal current source starts to charge CCDLY to an upper threshold using a fast ramp followed by a slow ramp. Several more ramps follow, during which time the device checks for fault conditions. If a fault is found, the sequence is halted. Initially the boost is not enabled so AVDD rises to VIN - VDIODE through the output diode. Hence, there is a step at AVDD during this part of the start up sequence. If this step is not desirable, an external PMOS FET can be used to delay the output until the boost is enabled internally. The delayed output appears at AVDD. AVDD soft-starts at the beginning of the third ramp. The softstart ramp depends on the value of the CDLY capacitor. The range of CDLY capacitor value is from 10nF to 220nF. For CDLY of 220nF, the soft-start time is ~8ms. VOFF turns on at the start of the fourth peak, at the same time DELB gate goes low to turn on the external PMOS to generate a delayed AVDD output. VON is enabled at the beginning of the sixth ramp. Once the start-up sequence is complete, the voltage on the CDLY capacitor remains at 1.15V until either a fault is detected or the EN pin is disabled. If a fault is detected, the voltage on CDLY rises to 2.4V at which point the chip is disabled until the power is cycled or enable is toggled.
RWhere Vg is the supply voltage applied to DRN or voltage at POUT, which range is from 0V to 36V. Ri is the resistance between COM and DRN or POUT including the internal MOSFET rDS(On), the trace resistance and the resistor inserted, RL is the load resistance of switch control circuit, and CL is the load capacitance of switch control circuit. In the "Typical Application Diagram" on page 10, R10, R11 and C15 give the bias to DRN based on Equation 22:
V ON R 11 +AVDD R 10 V DRN = -------------------------------------------------------------R 10 + R 11 (EQ. 22)
And R12 can be adjusted to adjust the slew rate.
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ISL97651
AVDD_delay Generation Using DELB
DELB pin is an open drain internal N-FET output used to drive an external optional P-FET to provide a delayed AVDD supply which also has no initial pedistal voltage (see Figure 15 and compare the AVDD and AVDD_delayed curves). When the part is enabled, the N-FET is held off until CDLY reaches the 4th peak in the start-up sequence. During this period, the voltage potential of the source and gate of the external P-FET (M0 in application diagram) should be almost the same due to the presence of the resistor (R4)
AVDD SOFT-START VREF, VLOGIC ON VOFF, DELB ON
across the source and gate, hence M0 will be off. Please note that the maximum leakage of DELB in this period is 500nA. To avoid any mis-trigger, the maximum value of R4 should be less than:
V GS ( th )_min(M0) R 4_max < ------------------------------------------500nA
(EQ. 23)
Where VGS(th)_min(M0) is the minimum value of gate threshold voltage of M0.
FAULT DETECTED tVON-SLICE NORMAL OPERATION VON SOFT-START
VCDLY
VIN EN VREF
VBOOST (AVDD) tSTART-UP tSS VLOGIC
VOFF
tVOFF DELAYED VBOOST (AVDD_delay) tVON VON
VON SLICE
NOTE: Not to scale
START-UP SEQUENCE TIMED BY CDLY
FAULT PRESENT
FIGURE 15. START-UP SEQUENCE
17
CHIP DISABLED
FN7493.2 March 15, 2007
ISL97651
After CDLY reaches the 4th peak, the internal N-FET is turned-on and produces an initial current output of IDELB_ON1 (~50A). This current allows the user to control the turn-on inrush current into the AVDD_delay supply capacitors by a suitable choice of C4. This capacitor can provide extra delay and also filter out any noise coupled into the gate of M0, avoiding spurious turn-on, however, C4 must not be so large that it prevents DELB reaching 0.6V by the end of the start-up sequence on CDLY, else a fault time-out ramp on CDLY will start. A value of 22nF is typically required for C4. The 0.6V threshold is used by the chip's fault detection system and if V(DELB) is still above 0.6V at the end of the power sequencing then a fault time-out ramp will be initiated on CDLY. When the voltage at DELB falls below ~0.6V it's current is increased to IDELB_ON2 (~1.4mA) to firmly pull the DELB voltage to ground. If the maximum VGS voltage of M0 is less than the AVDD voltage being used, then a resistor may be inserted between the DELB pin and the gate of M0 such that it's potential divider action with R4 ensures the gate/source stays below VGS(M0)max. This additional resistor allows much larger values of C4 to be used, and hence longer AVDD delay, without affecting the fault protection on DELB.
Layout Recommendation
The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF and VDC bypass capacitors close to the pins. 3. Reduce the loop with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point. 6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC." 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. Minimize feedback input track lengths to avoid switching noise pick-up. A demo board is available to illustrate the proper layout implementation.
Component Selection for Start-up Sequencing and Fault Protection
The CREF capacitor is typically set at 220nF and is required to stabilize the VREF output. The range of CREF is from 22nF to 1F and should not be more than five times the capacitor on CDEL to ensure correct start-up operation. The CDEL capacitor is typically 220nF and has a usable range from 47nF minimum to several microfarads - only limited by the leakage in the capacitor reaching A levels. CDEL should be at least 1/5 of the value of CREF (see above). Note with 220nF on CDEL the fault time-out will be typically 50ms and the use of a larger/smaller value will vary this time proportionally (e.g., 1F will give a fault time-out period of typically 230ms).
Over-Temperature Protection
An internal temperature sensor continuously monitors the die temperature. In the event that the die temperature exceeds the thermal trip point of +150C, the device will shut down. Operation with die temperatures between +125C and +150C can be tolerated for short periods of time, however, in order to maximize the operating life of the IC, it is recommended that the effective continuous operating junction temperature of the die should not exceed +125C.
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FN7493.2 March 15, 2007
ISL97651 Thin Quad Flat No-Lead Plastic Package (TQFN)
2X A D D/2 0.15 C A
L36.6x6
36 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C) MILLIMETERS SYMBOL
2X
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
A
0.15 C B
6 INDEX AREA
N 1 2 3 E/2 E
A1 A3 b D D2 E
0.18
0.25 6.00 BSC
0.30
5, 8 -
3.80
3.95 6.00 BSC
4.05
7, 8 -
TOP VIEW
B
E2 e k
A
3.80
3.95 0.50 BSC
4.05
7, 8 -
0.20 0.45
0.55 36 9 9
0.65
8 2 3 3 Rev. 2 04/06
L
/ / 0.10 C 0.08 C
C
N Nd Ne
SEATING PLANE
SIDE VIEW
A3
A1
NX b D2 D2 2
5 0.10 M C A B 7 8 NX k N
(DATUM B)
(DATUM A) (Ne-1)Xe REF. 8
6 INDEX AREA
E2 3 2 1 NX L N 8 e (Nd-1)Xe REF. BOTTOM VIEW E2/2
7
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
A1 NX b 5
SECTION "C-C"
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN7493.2 March 15, 2007

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